Fault Coverage Evaluation of Protocol Test Sequences

In this paper, we investigate the quality of a given protocol test sequence in detecting faulty implementations of the specification. The underlying model is a deterministic finite state machine (FSM). The basic idea is to construct all FSMs having n + i states (where n is the number of states in the specification and i a small integer) that will accept the test sequence but do not conform to the specification. It differs from the conventional simulation method in that it is not necessary to consider various forms of fault combinations and is guaranteed to identify any faulty machines. Preprocessing and backjumping techniques are used to reduce the computational complexity. We have constructed a tool based on the model and used it in assessing several UIO-based optimization techniques. We observed that the use of multiple UIO sequences and overlaps can sometimes weaken the fault coverage of the test sequence. The choice of the transfer sequences and order of the test subsequences during optimization may also affect fault coverage. Other observations and analysis on the properties of test sequences are also made.