A New Golden Age for Computer Architecture - DLS Talk by David Patterson (UC Berkeley)

Date: 
Thursday, May 16, 2019 | 3:30pm - 5:00pm
Location: 
Hugh Dempster Building (6245 Agronomy Rd), Room 110

David PattersonSpeaker:  Dr. David A. Patterson, Pardee Professor of Computer Science, Emeritus at the University of California at Berkeley

Title:  A New Golden Age for Computer Architecture

Abstract:

In the 1980s, Mead and Conway democratized chip design and high-level language programming surpassed assembly language programming, which made instruction set advances viable.  Innovations like Reduced Instruction Set Computers (RISC), superscalar, and speculation ushered in a Golden Age of computer architecture, when performance doubled every 18 months. The ending of Dennard Scaling and Moore’s Law crippled this path; microprocessor performance improved only 3% last year!  In addition to poor performance gains of modern microprocessors, Spectre recently demonstrated timing attacks that leak information at high rates. The ending of Dennard scaling and Moore's law and the deceleration of performance gains for standard microprocessors are not problems that must be solved but facts that if accepted offer breathtaking opportunities.  We believe high-level, domain-specific languages and architectures, freeing architects from the chains of proprietary instruction sets and the demand from the public for improved security will usher in a new Golden Age.  Aided by open source ecosystems, agilely developed chips will convincingly demonstrate advances and thereby accelerate commercial adoption.  The instruction set philosophy of the general-purpose processors in these chips will likely be RISC, which has stood the test of time.  We envision the same rapid improvement as in the last Golden Age, but this time in cost, energy, and security as well as in performance. Like in the 1980's, the next decade will be exciting for computer architects in academia and in industry!

Bio:

David Patterson is a professor emeritus of Computer Science at UC Berkeley, a distinguished engineer at Google, and Vice-Chair of the Board of Directors of the RISC-V Foundation.  He received his BA, MS, and PhD degrees from UCLA.  His most successful research projects were likely Reduced Instruction Set Computer (RISC), Redundant Array of Inexpensive Disks (RAID), and Network of Workstation (NOW).  All three projects helped lead to multibillion-dollar industries. This research led to many papers and seven books, with the best known being Computer Architecture: A Quantitative Approach co-authored by John Hennessy, now in its sixth edition.  His most recent book is The RISC-V Reader: An Open Architecture Atlas, co-authored by Andrew Waterman.  Patterson is a member of the National Academy of Engineering, the National Academy of Sciences, and the Silicon Valley Engineering Hall of Fame.  His teaching was honored with the ACM Karlstrom Award and the IEEE Mulligan Medal.  As a past president of ACM and a past Chair of CRA, he received Distinguished Service Awards from ACM, CRA, and SIGARCH and the Tapia Achievement Award for Scientific Scholarship, Civic Science, and Diversifying Computing. His most recent award is the ACM A.M Turing Award, shared with John Hennessy, which is the highest award in computer science.          


Sponsors

1QBit         Pacific Institute for the Mathematical Sciences


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