Simple Machine

Arch.Y86.Machine.Pipe.Solution
Class CPU

java.lang.Object
  extended by java.util.Observable
      extended by Machine.AbstractCPU
          extended by Arch.Y86.Machine.AbstractY86CPU
              extended by Arch.Y86.Machine.Pipe.Solution.CPU

public class CPU
extends AbstractY86CPU


Nested Class Summary
 
Nested classes/interfaces inherited from class Arch.Y86.Machine.AbstractY86CPU
AbstractY86CPU.DecodeStageState, AbstractY86CPU.ExecuteStageState, AbstractY86CPU.FetchStageState, AbstractY86CPU.MemoryStageState, AbstractY86CPU.ProcessorState, AbstractY86CPU.StageState, AbstractY86CPU.WriteBackStageState
 
Nested classes/interfaces inherited from class Machine.AbstractCPU
AbstractCPU.InvalidInstructionException, AbstractCPU.MachineHaltException
 
Field Summary
 
Fields inherited from class Arch.Y86.Machine.AbstractY86CPU
A_ADDL, A_ANDL, A_SUBL, A_XORL, BUBBLE, d, e, f, I_CALL, I_HALT, I_IADDL, I_IRMOVL, I_JMPI, I_JXX, I_LEAVE, I_MRMOVL, I_NOP, I_OPL, I_POPL, I_PUSHL, I_RET, I_RMMOVL, I_RRMOVL, J_E, J_G, J_GE, J_L, J_LE, J_NC, J_NE, m, NORMAL, p, R_EBP, R_ESP, R_NONE, STALL, w
 
Fields inherited from class Machine.AbstractCPU
CURRENT_INSTRUCTION_ADDRESS, isInterrupt, mem, PC, processorState, reg
 
Constructor Summary
CPU(MainMemory aMem)
           
 
Method Summary
protected  void cycle()
          Execute one clock cycle with all stages executing in parallel.
protected  void decode()
          The DECODE stage of CPU
protected  void execute()
          The EXECUTE stage of CPU
protected  void fetch_SelectPC()
          The part of the FETCH that selects the PC of the instruction to fetch.
protected  void fetch()
          The FETCH stage of CPU Reads the PC from the input port of the f.pc register.
protected  void memory()
          The MEMORY stage of CPU
protected  void pipelineHazardControl()
          Pipeline Hazard Control Logic
protected  void writeBack()
          The WRITE BACK stage of CPU
 
Methods inherited from class Arch.Y86.Machine.AbstractY86CPU
createDecodeStageState, createExecuteStageState, createFetchStageState, createMemoryStageState, createProcessorState, createWriteBackStageState, cyclePipe, cycleSeq, nextPC, setPC
 
Methods inherited from class Machine.AbstractCPU
getMainMemory, getName, getPC, getProcessorState, getRegisterFile, start, triggerInterrupt
 
Methods inherited from class java.util.Observable
addObserver, clearChanged, countObservers, deleteObserver, deleteObservers, hasChanged, notifyObservers, notifyObservers, setChanged
 
Methods inherited from class java.lang.Object
clone, equals, finalize, getClass, hashCode, notify, notifyAll, toString, wait, wait, wait
 

Constructor Detail

CPU

public CPU(MainMemory aMem)
Method Detail

cycle

protected void cycle()
              throws AbstractCPU.InvalidInstructionException,
                     AbstractMainMemory.InvalidAddressException,
                     AbstractCPU.MachineHaltException
Execute one clock cycle with all stages executing in parallel.

Specified by:
cycle in class AbstractCPU
Throws:
InvalidInstructionException - if instruction is invalid (including invalid register number)
AbstractMainMemory.InvalidAddressException - if instruction attemps an invalid memory access (either instruction or data)
MachineHaltException - if instruction halts the CPU
AbstractCPU.InvalidInstructionException
AbstractCPU.MachineHaltException

pipelineHazardControl

protected void pipelineHazardControl()
Pipeline Hazard Control Logic

Overrides:
pipelineHazardControl in class AbstractY86CPU

fetch_SelectPC

protected void fetch_SelectPC()
The part of the FETCH that selects the PC of the instruction to fetch. Writes the selected PC into the f.pc register.

Overrides:
fetch_SelectPC in class AbstractY86CPU

fetch

protected void fetch()
              throws AbstractCPU.InvalidInstructionException,
                     AbstractMainMemory.InvalidAddressException
The FETCH stage of CPU Reads the PC from the input port of the f.pc register.

Specified by:
fetch in class AbstractY86CPU
Throws:
InvalidInstructionException - if instruction opcode or format is invalid
AbstractMainMemory.InvalidAddressException - if current pc is invalid
AbstractCPU.InvalidInstructionException

decode

protected void decode()
               throws RegisterSet.InvalidRegisterNumberException
The DECODE stage of CPU

Specified by:
decode in class AbstractY86CPU
Throws:
RegisterSet.InvalidRegisterNumberException - if instruction attempts to access register number > 7

execute

protected void execute()
The EXECUTE stage of CPU

Specified by:
execute in class AbstractY86CPU

memory

protected void memory()
               throws AbstractMainMemory.InvalidAddressException
The MEMORY stage of CPU

Specified by:
memory in class AbstractY86CPU
Throws:
AbstractMainMemory.InvalidAddressException - if instruction attempts to access an invalid memory address

writeBack

protected void writeBack()
                  throws AbstractCPU.MachineHaltException,
                         RegisterSet.InvalidRegisterNumberException
The WRITE BACK stage of CPU

Specified by:
writeBack in class AbstractY86CPU
Throws:
MachineHaltException - if instruction halts the CPU (e.g., halt instruction)
RegisterSet.InvalidRegisterNumberException - if instruction attempts to access register number > 7
AbstractCPU.MachineHaltException

Simple Machine