ResearchI am dedicated to researching better ways of designing integrated circuits such that the number of defects (bugs) can be reduced resulting in cheaper design costs. In particular, my interests relate to techniques applied to verification of hardware designs. I describe below the motivation for my work. Hopefully, it is easy to read and interesting to you! Verification of Hardware Designs Verification of integrated circuits (IC)-- Application-Specific Integrated Circuits -- is the most important task in designing an IC. Tighter time-to-market and increased feature requirements coupled with higher quality expectations are the major contributors to the complexity of today's design. As a result, the semiconductor industry is observing a fast paced increase in the verification effort, which is measured not only by design time (70% dedicated to verification) but also the by the number of required verification engineers in a design team. You might ask, "What do you actually mean by hardware verification? Hardware verification is the process of validating a design before it becomes silicon (an actual chip). Therefore, it entails verifying a model of the intended hardware. Traditionally, hardware verification has been done by simulating test vectors (sequences of zero and ones) and checking if the model behaves as expected. However, simulation never guarantees a bug-free design. Why? One of the reasons is that simulation is ten-thousand or more times slower than the hardware. Simulating a few seconds of real hardware takes weeks/months depending on the design. In other words, it is only possible to validate a small fraction of the design's behavior. To counter this problem, new verification techniques have been explored since the beginning of the 90's. These new techniques use mathematical reasoning to prove that a design is correct. Because of this formalism, these techniques are known as formal verification. The good thing about formal verification is that it allows engineers to verify more behavior than simulation. The bad thing is the limitation on the design's size that it can verify. A design's size can be measured by its state space. The state space is a function of the number of storage elements a design contains. Each storage element can hold values zero or one. Thus, state space is 2^n (2 to the power of n), where n is the number of storage elements. Because our technology has been improving so fast, the state space of a design can be as big as the number of stars in the Universe! Unfortunately, there is not enough memory in today's computer to store this number of states. Given the limitations of both simulation and formal verification techniques, my research intends to investigate and explore their synergy and use the best of each technique to verify state-of-the-art industrial designs. More specifically, here is a list of some of my interests (not necessarily in this order):
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