EverLost Benchmarks
Copyright (C) 2006-2007  Flavio M. de Paula

README:
------

1- Introduction:

This is a benchmark based on the USB 2.0 Packet Layer unit, a  unit of
the USB 2.0 Function Core from opencores.org.

Since VCEGAR supports only a sub-set of synthesizable Verilog, I had 
to modify the code making it compatible with VCEGAR.

All changes were tagged. Please, see TAG_Changes file for description of
the tags.

I used Synopsys Formality to check equivalence between the modified code
and the original one from opencores.org. Formality reports 'success' along
with a list of the extra ports required to make signals observable by VCEGAR
(See Tag_Changes, FMP_VC_0 for explanation). Therefore, to the best of my 
knowledge and use of resources available the functionality of these models 
are equivalent.


2- Directory structure:

./mod: 
Directory containing modified model;

./org: 
Directory containing original model;

./benchmarks: 
Directory containing the benchmarks (in the following sub-directories):

  usb_p0, usb_p1, usb_p2, usb_p3:
  source files and property file

  usb_p0_results, usb_p1_results, usb_p2_results, usb_p3_results:
  output from vcegar along with b*.log, a transcript file with the output
  of the vcegar run;

