EverLost Benchmarks
Copyright (C) 2006-2007  Flavio M. de Paula

README:
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1- Introduction:

This is a benchmark based on the core units of the ETHERNET MAC 10/100Mbits
from opencores.org.

Since VCEGAR supports only a sub-set of synthesizable Verilog, I had 
to modify the code making it compatible with VCEGAR.

All changes were tagged. Please, see TAG_Changes file for description of
the tags.

I used Synopsys Formality to check equivalence between the modified code
and the original one from opencores.org. Formality reports 'success' along
with a list of the extra ports required to make signals observable by VCEGAR
(See TAG_Changes, FMP_VC_0 for explanation). Therefore, to the best of my 
knowledge and use of resources available the functionality of these models 
are equivalent.


2- Directory structure:

./mod: 
Directory containing modified model;

./org: 
Directory containing original model;

./benchmarks: 
Directory containing the benchmarks (in the following sub-directories):

  eth_p0, eth_p1:
  source files and property file

  eth_p0_results, eth_p1_results:
  output from vcegar along with b*.log, a transcript file with the output
  of the vcegar run;


3- Benchmarks Description:

eth_p0: "RxEndFrm = True", that is, once the PHY receives data, and assembles it
into a transaction, does the Receive Interface signals the end of the 
trasaction to the uplink?

eth_p1: "CrcHashGood = True", that is, is the received CRC ever latched?
   
