EverLost Benchmarks
Copyright (C) 2006-2007  Flavio M. de Paula

This file contains the description of the tags used in all of
the files listed in the mod directory.

Tags:
----
 
FMP_VC_0: 
Bringing up signal to be observable in vcegar property file.

FMP_VC_1:
vcegar has issue with buses on ports and their use at the
higher levels in the hierarchy.

FMP_VC_2:
vcegar does not handle properly Verilog token 'parameter'.

FMP_VC_3:
vcegar does not handle bus definition (wire [n:0] sig1) and 
its later use with the Verilog token 'assign' 
(assign sig1 = ...).

FMP_VC_4:
vcegar requires the Verilog 'initial' statement to initialize
latches.

FMP_VC_5:
vcegar requires Verilog 'case' statements to have 'default'
statement.

FMP_VC_6:
vcegar seems to not support arithmetic in bus signal definition.

FMP_VC_7:
vcegar does not support casex.

FMP_VC_8:
vcegar does not support latch assignments to parts of a bus.

FMP_VC_9:
vcegar does not support multi-clock; hard-wiring to single clk (may not
be necessary because hard-wiring at a higher-level in the hierarchy.

FMP_VC_10: vcegar seems to not be able to parse this nested construct.

FMP_VC_11: vcegar seems to not be able to parse LHS with 'range'.