EverLost Benchmarks
Copyright (C) 2006-2007  Flavio M. de Paula

README:
------

1- Introduction:

This directory contain the benchmarks (examples) used in [1].

Since VCEGAR supports only a sub-set of synthesizable Verilog, I had 
to modify the code making it compatible with VCEGAR.

All changes were tagged. Please, see TAG_Changes file for description of
the tags.

I used Synopsys Formality to check equivalence between the modified code
and the original one from opencores.org. Formality reports 'success' along
with a list of the extra ports required to make signals observable by VCEGAR
(See TAG_Changes, FMP_VC_0 for explanation). Therefore, to the best of my 
knowledge and use of resources available the functionality of these models 
are equivalent.


2- Top Directory structure:

./License and ./lgpl.txt
Licensing terms.

./README
This file.

./ethernet
Directory containing Ethernet benchmarks.

./usb
Directory containing USB benchmarks.


3- Reference:

[1] 
@inproceedings{depaula-hu-dac07,
 author =     {Flavio M. de Paula and Alan J. Hu},
 title =      {An Effective Guidance Strategy for Abstraction-Guided Simulation},
 booktitle =  {Design Automation Conference (DAC)},
 address =    {San Diego, CA},
 month =      {June 4--8},
 year =       {2007},
}
