| Jan. 10: | Course overview |
| Jan. 12: | Computer Organization and Design, J.L. Hennessy and D.A. Patterson, chapter 3.1-3.5, 3.12. |
| Optional:"Architecture of the IBM System/360", G.M. Amdahl, G.A. Blaaw, and F.P. Brooks Jr. | |
| Jan. 17: | "The Case for the Reduced Instruction Set Computer", D.A. Patterson and D.R. Ditzel, ACM SIGARCH Computer Architecture News, vol. 8, no. 6 (Oct. 1980), pp. 25-33. |
| "Instructions Sets and Beyond: Computers, Complexity, and Contraversy", R.P. Colwell, C.Y. Hitchcock III, et al., IEEE Computer, vol. 18, no. 9 (Sept. 1985), pp. 8-19. | |
| Optional: "Comments on `The Case for the Reduced Instruction Set Computer", D.W. Clark and W.D. Strecker, ACM SIGARCH Computer Architecture News, vol. 8, no. 6 (Oct. 1980), pp. 34-38. | |
| Jan. 19: | "MIPS-X: A 20-MIPS Peak, 32-bit Microprocessor with On-Chip Cache", M.A. Horowitz, P. Chow, et al., IEEE Journal of Solid State Circuits, vol. 22, no. 5 (Oct. 1987), pp. 790-799. |
| Optional: "Alpha AXP Architecture", R.L.\ Sites, Communications of the ACM, vol. 36, no. 2 (Feb. 1993), pp. 33-44 | |
| Jan. 24: | "Structural Aspects of the System/360 Model 85, Part II: The Cache", J.S. Liptay, IBM Systems Journal, vol. 7, no. 1, pp. 15-21, 1968. |
| "Improving direct-mapped cache performance by the addition of a small, fully-associative cache and prefetch buffers", N.P. Jouppi, Proceedings of the 17th Annual International Symposium on Computer Architecture, pp. 364-373, May 1990. | |
| Optional: "Slave memories and dynamic storage allocation", M.V. Wilkes, IEEE Transactions on Electronic Computers, vol. EC-14, no. 2, pp. 270-271, 1965. | |
| Jan. 26: | "Organization and performance of a Two-Level Virtual-Real Cache Hierarchy", W.-H. Wang, J.-L. Baer, and H.M. Levy, Proceedings of the 16th Annual International Symposium on Computer Architecture, pp. 140-148, May 1989. |
| Jan. 31: | "Machine Organization of the IBM RISC System/6000 Processor", G.F. Grohoski, IBM Journal of Research and Development, vol. 34, no. 1, pp. 34-58, Jan. 1990. |
| "The MIPS R10000 Superscalar Microprocessor", K.C. Yeager, IEEE Micro, vol. 16, no. 2, pp. 28-40, Apr. 1996. | |
| Feb. 2: | "A 0.18 micron CMOS IA-32 processor with a 4-GHz integer execution unit", G. Hinton, M. Upton, et al., IEEE Journal of Solid State Circuits, vol. 36, no. 11, Nov. 2001, pp. 1617-1627. |