| January 10 |
The Landscape of Parallel Computing Research: A View from Berkeley, K. Asanovic et al., pages 1-19. |
| Jan. 12 |
The Landscape of Parallel Computing Research: A View from Berkeley, K. Asanovic et al., pages 20-27, 31-45. |
| Jan. 15 |
The Case for the Reduced Instruction Set Computer, D.A. Patterson and D.R. Ditzel. |
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Instructions Sets and Beyond: Computers, Complexity, and Controversy, R.P. Colwell, C.Y. Hitchcock III, et al., IEEE Computer, September, 1985, pp. 8-19. |
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Comments on ``The Case for the Reduced Instruction Set Computer'', D.W. Clark and W.D. Strecker.(optional) |
| Jan. 17 |
A 32-Bit VLSI CPU with 15 MIPS Peak Performance, M. Forsyth, W.S. Jaffe, et al., IEEE Journal of Solid State Circuits, vol. SC-22, no. 5, October, 1987, pp. 768-775 |
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The Pentium Chronicals: Introduction, R.P. Colwell, IEEE Computer, Jan. 2006, pp. 49-54. |
| Jan. 19 |
Computer Architecture: A Quantitative Approach (2nd edition, pp. 372-411) John L. Hennessy and David A. Patterson, pp.375-393. |
| Jan. 21 |
The MIPS R1000 Superscalar Microprocessor K.C. Yeager, IEEE Micro, vol. 16, no. 2, pp. 28-40,
Apr. 1996. |
| Jan. 24 |
A 0.18μm CMOS IA-32 Processor with a 4GHz Integer Execution Unit IEEE Journal of Solid State Circuits,
vol. 36, no. 11, Nov. 2001, pp. 1617-1627. |
| Jan. 25 |
The Cosmic Cube |
| Jan. 26 |
The Limits of Instruction Level Parallelism, David Wall. |
| Feb. 2 |
A Message Passing Standard for MPP and Workstations |
| Feb. 5 |
Using Cache Memory to Reduce Processor Memory Traffic |
| Feb. 7 |
The Sun Fireplane SMP Interconnect in the Sun Fire 3800-6800 |
| Feb. 9 |
OpenMP: An Industry-Standard API for Shared-Memory Programming |
| Mar. 2 |
Energy
dissipation in general purpose microprocessors |
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Power:
a first-class architectural design constraint |
| Mar. 5 |
Dynamic
frequency and voltage scaling for a multiple-clock-domain
microprocessor |
| Mar. 7 |
Exploiting
choice: instruction fetch and issue on an implementable simultaneous
multithreading processor |
| Mar. 9 |
The
case for a single-chip multiprocessor |
| Mar. 19 |
Piranha:
A Scalable Architecture Based on Single-Chip Multiprocessing |
| Mar. 21 |
Niagra:
A 32-Way Multithreaded Sparc Processor |
| Mar. 23 |
Hyper-Threading
Technology Architecture and Microarchitecture |
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Initial
Observations of the Simultaneous Multithreading
Pentium 4 Processor |
| Mar. 26 |
Synergistic
Processing in Cell's Multicore Architecture |
| Mar. 28 |
Optimizing
Compiler for a CELL Processor |
| Mar. 30 |
The
potential of the cell processor for scientific computing |
| April 2 |
The future of nanocomputing
OR Supertubes [carbon nanotubes] |
| April 5 |
NanoFabrics: spatial computing using molecular electronics
OR Array-based architecture for FET-based, nanoscale electronics |
| April 23 | FINAL EXAM |
|
Evaluation
of the Raw microprocessor: an exposed-wire-delay architecture
for ILP and streams |
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