I'm now a Ph.D. candidate of Integrated Systems Design Laboratory, Computer Science Department at University of British Columbia. Supervised by Mark R. Greenstreet. I will graduate soon and therefore I am looking for a position in a research lab or academia. My resume is available here.
I received my MS degree and Ph.D. degree in Department of Computer Science from University of British Columbia, Canada and BS degree in Department of Computer Science from Peking University, P.R.China.
Coho is a reachability analysis tool specified for analog or mixed signal circuits verification.
Chao Yan, Mark Greenstreet, ``Oscillator Verification with Probability One'', Proceedings of the 12th Conference on Formal Methods in Computer Aided Design (FMCAD), October, 2012, pp 165-172. [pdf, slides, bib]
Chao Yan, ``Reachability Analysis Based Circuit-Level Formal Verification'', Ph.D Dissertation in the University of British Columbia, November, 2011, [pdf, slides, bib]
Chao Yan, Mark Greenstreet, ``Circuit-Level Verification of Practical Circuits Based on Reachability Analysis'', Frontiers in Analog Circuit (FAC) Synthesis and Verification, July, 2011, [pdf, slides, bib]
Chao Yan, Florent Ouchet, Laurent Fesquet, Katell Morin-Allory, ``Formal Verification of C-element Circuits'', The 17th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), April, 2011. (Acceptance rate 29%) [pdf, slides, bib]
Chao Yan, Mark Greenstreet, Jochen Eisinger, ``Formal Verification of Arbiters'', The 16th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May, 2010. (Acceptance rate 32%) [pdf, slides, bib]
Chao Yan, Kevin Jones, ``Efficient Simulation Based Verification by Reordering'', DVCon, February, 2010. (Acceptance rate 39/123, 31.7%) [pdf, slides, bib]
Chao Yan, Mark Greenstreet, ``Verifying an Arbiter Circuit'', Proceedings of the 8th Conference on Formal Methods in Computer Aided Design (FMCAD), November, 2008, pp 52-60. (Acceptance rate 24/61, 39.3%) [pdf, slides, bib]
Chao Yan, Mark Greenstreet, ``Faster Projection Based Methods for Circuit Level Verification'', Proceedings of the 13th Asia South Pacific Design Automation Conference (ASP-DAC), 2008, pp 410-415. (Acceptance rate 100/350, 28.5%) [pdf, slides, bib]
Chao Yan, Mark Greenstreet, ``Circuit Level Verification of a High-Speed Toggle'', Proceedings of the 7th Conference on Formal Methods in Computer Aided Design (FMCAD), November, 2007, pp 199-206. (Acceptance rate 23/65, 35.3%) [pdf, slides, bib]
Chao Yan, ``Coho: A Verification Tool for Circuit Verification by Reachability Analysis'', Master Dissertation in the University of British Columbia, November, 2006, [pdf, slides, bib]
Chao Yan, Mark Greenstreet, Marius Laza, ``A Robust Linear Program Solver for Reachability Analysis'', Mathematical Aspects of Computer and Information Sciences (MACIS), July, 2006, pp 231-242. [pdf, slides, bib]