Simultaneous enjoyment of Whistler mountain and Seattle's Best Coffee. Photo By Kelly Sung.
Welcome to my web page!
I am a computer science PhD student at UBC, supervised by Mark Greenstreet. I am a member of the Integrated Systems Design Lab, located in ICICS/CS room 342. I did my B.Sc. at UVic in combined computer science and mathematics, and my MSc. in computer science at UBC. My interests, master's thesis description and other miscellanea are below.

Thesis

My thesis is titled: Energy-Time Complexity of Algorithms: Modelling the Trade-offs of CMOS VLSI. You can find it online here. Here's a brief motivation and description:

Traditional algorithm analysis and design measures performance by counting the number of operations performed by a sequential processor. Modern processors are limited by power dissipation rather than speed, and this is likely to remain a critical bottleneck in processor design. In practice, operation count and energy consumption have a trade-off relationship. In particular, if more time is given for a hardware computation, the total energy required can be reduced by employing a technique known as voltage scaling. This creates a strong incentive for exploiting parallelism: a parallel algorithm may use less energy than a sequential version that completes the computation in the same amount of time even if the parallel algorithm performs more operations, as more time can be given for each operation. Although parallel algorithms have been studied extensively, we are not aware of any prior work that models this fundamental trade-off between time and energy. This is the focus of my research.

To capture the trade-offs found in current computation devices, we developed a model that allows unlimited parallelism as an abstraction of the large number of transistors that can be integrated onto a single chip. Unlike many other models, we charge for communication because wires on chips account for a large fraction of the total power consumption and delay. We restrict the graph of components and wires to reflect a planar embedding of the computation. We allow a trade-off between energy and time on a per-operation and per-wire basis. Let e be the energy required for a primitive operation and t be the time. In our model, et^2 is a constant that depends on the particular operation; this represents the scaling in a simplified physical model for CMOS logic gates. We seek ET^2 optimal algorithms, where E is the total energy used when performing the algorithm, and T is the total time.

Interests

My interests span many areas of which my understanding varies wildly. Therefore, I make no claim to be an expert of all (or any!) of the following topics. I've linked some of these to their wikipedia pages, which has a far better explanation than I could give. Here's the non-exhaustive list:

Courses

Fall 2008:
Spring 2007:
Fall 2006:
Spring 2006: Fall 2005:

Selected Publications

Bingham, Brad D., and Mark R. Greenstreet, "Energy optimal scheduling on multiprocessors with migration", IEEE International Symposium on Parallel and Distributed Processing with Applications (ISPA08), to appear.

Bingham, Brad D., and Mark R. Greenstreet, "Computation with energy-time trade-offs: models, algorithms and lower bounds", IEEE International Symposium on Parallel and Distributed Processing with Applications (ISPA08), to appear.

Bingham, Jesse, and Brad Bingham, "Hybrid one-dimensional reversible cellular automata are regular", Discrete Applied Mathematics, v. 155 n. 18, pp. 2555-2566, 2007.

Bingham, B.D., D.D. Olesky, and P. van den Driessche, "Potentially nilpotent and spectrally arbitrary even cycle sign patterns", Linear Algebra and its Applications, 421, pp. 24-44, 2007.

Contact

Email: