The design of Very Large Scale Integrated (VLSI) circuits remains an art despite recent advances in Computer Assisted Design (CAD) techniques. Unfortunately, the sophistication of the design procss has not kept pace with the VLSI hardware technology. Very expensive errors proliferate into fabrication despite powerful design rule checkers and circuit simulators. We have developed an alternative approach derived from research in knowledge representation and schema-based computer vision. The system implemented recognizes an abstract logic function description of the VLSI circuit from its mask layout artwork. Our technique reverses the desiFn process thereby recovering the logical function actually fabricated in the chip. No simulation is necessary and conceptually all logical design errors can be detected. The work is a direct application of schema labelling techniques which were developed for the Mapsee2 sketch map understanding system. This prototype system has been tested on a number of logical chip designs with correct results. Some results are presented.
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